The present invention relates to a chip size package and a method of manufacturing the same and, more particularly, to the package structure of a chip size package for portable information devices which must be mounted at high densities, and a method of manufacturing the same.
In recent years, compact information devices such as a PHS (Personal Handyphone System) and a PDA (Personal Digital Assistant) are actively being developed. Since these devices are very small, and their mounting spaces are limited, downsizing and an increase in density are also required for semiconductor packages to be used.
To meet these requirements, for example, a chip size package (to be referred to as a CSP hereinafter) mountable with almost the same size as that of a chip on which a semiconductor integrated circuit is formed is proposed. There are some types of conventional CSPs, and examples of the CSP will be described below.
FIG. 8 is a sectional view showing the first example of the conventional CSP structure. As shown in FIG. 8, a chip 100 is connected to a ceramic base 102 via plated bumps 101. Solder bumps 103 are formed at lower portions of the base 102. The connected portion by the plated bumps 101 is sealed by a potting agent 104 or the like.
FIG. 9 is a sectional view showing the second example of the conventional CSP structure. As shown in FIG. 9, a chip 110 is connected to a ceramic base 113 via stud bumps 111 made of, e.g., gold and a conductive paste 112 for fixing the stud bumps 111. Similar to the first example, solder bumps 114 are formed at lower portions of the base 113. The connected portion by the stud bumps 111 and the conductive paste 112 is sealed by a potting agent 115 or the like. The second example is different from the first example in that the chip and the base are connected via the plated bumps 101 in the first example, whereas they are connected via the stud bumps 111 and the conductive paste 112 in the second example.
FIG. 10 is a sectional view showing the third example of the conventional CSP structure. As shown in FIG. 10, a chip 120 is connected to inner leads 123 of a TAB (Tape Automated Bonding) tape 122 via plated bumps 121. Solder bumps 124 are formed at lower portions of the TAB tape 122. The connected portion by the plated bumps 121 and the inner leads 123 is sealed by a potting agent 125 or the like.
Each chip size package (CSP) described above however suffers some problem in terms of downsizing and manufacturing. In the first example, since a resin must be filled in the connected portion between the chip 100 and the base 102 by capillary action, sealing by potting must be performed every product, resulting in poor productivity. The base 102 used is generally made of ceramic. Since the ceramic becomes very hard upon calcination, processing such as cutting is difficult to perform in the assembly step. Therefore, the base 102 must be loaded to the assembly step in the form of a single piece, and the base 102 must be set/removed on/from a convey jig and the like, which further decreases the productivity.
In the second example, similar to the first example, sealing by potting must be performed for every product, and the base 113 must be set/removed on/from a convey jig and the like, resulting in poor productivity.
In the third example, the TAB tape 122 must be smaller in size than the chip 120, so the formation area for the solder bumps 124 is small. Even if the chip has the same number of pins as those in the first and second examples, the chip is difficult to mount because the pitch between the solder bumps 124 is smaller.